Method and Apparatus for Reading a Programmable Anti-Fuse Element in a High-Voltage Integrated Circuit

ABSTRACT

A semiconductor device comprises an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which comprises the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET. This abstract is provided to allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

TECHNICAL FIELD

The present disclosure generally relates to semiconductor processes forfabricating high-voltage integrated circuits with programmableelectrical connections.

BACKGROUND

A common type of integrated circuit (IC) device is ametal-oxide-semiconductor field effect transistor (MOSFET). A MOSFET isa field-effect device that includes a source region, a drain region, achannel region extending between the source and drain regions, and agate provided over the channel region. The gate includes a conductivegate structure disposed over the channel region. The conductive gate istypically insulated from the channel region by a thin oxide layer.

High-voltage, field-effect transistors (HVFETs) are also well known inthe semiconductor arts. Many HVFETs employ a device structure thatincludes an extended drain region that supports or “blocks” the appliedhigh-voltage (e.g., 200 volts or more) when the device is in the “off”state. Conventional HVFETs are commonly formed as lateral or verticaldevice structures. In a lateral HVFET, current flow in the on-state ishorizontal or substantially parallel to a surface of the semiconductorsubstrate. On the other hand, in a vertical HVFET current flowsvertically through the semiconductor material, e.g., from a top surfaceof the substrate where the source region is disposed, down to the bottomof the substrate where the drain region is located.

Conventional power IC devices often employ a large vertical or lateralhigh-voltage output transistor in a configuration wherein the drain ofthe output transistor is coupled directly to an external pin. The powerIC device typically includes a controller circuit that is separate fromthe high-voltage output transistor. Both the controller and outputtransistor are usually housed in the same IC package. To providestart-up current for the controller circuit of the IC, a high externalvoltage may be applied to the external pin. The controller is typicallylimit-protected from the high externally-applied voltage by a junctionfield-effect transistor (JFET) “tap” structure. For example, when thedrain of the high voltage output transistor is taken to, say 550V, thetap transistor limits the maximum voltage coupled to the controller toapproximately 50V, thereby providing a small (2-3 mA) current forstart-up of the device. By way of further background, U.S. Pat. No.7,002,398 discloses a three-terminal JFET transistor that operates inthis manner.

The operating characteristics of a power IC device is typically set orprogrammed by selectively opening (or closing) one or more electricalconnections. A zener diode is one type of electrical element used totrim or program analog parameters (e.g., frequency) of a power ICdevice. A zener diode provides a normally off or non-conductingelectrical connection. To change the conducting state of the zenerelement a high voltage (>10V) is typically applied to breakdown thezener, with the large resulting current (150-200 mA) shorting the anodeand cathode terminals of the zener permanently. The cumulative currentflowing through the zener elements may be used to program one or moreanalog parameters. For example, based on the state of one or more zenerelements, an analog parameter such as frequency may be set within aspecified tolerance in the controller section of the power IC.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and notlimitation, in the figures of the accompanying drawings, wherein:

FIG. 1 illustrates an example power IC device block diagram.

FIG. 2 illustrates an example cross-section of an anti-fuse structure.

FIG. 3 illustrates an example circuit schematic diagram of an anti-fusetrimming architecture for a power IC.

FIG. 4 illustrates an example cross-section of a programming elementcomprising an integrated transistor and anti-fuse device structure.

FIG. 5 is an equivalent circuit schematic diagram of the integrateddevice structure shown in FIG. 4.

FIG. 6 illustrates another example circuit schematic diagram of ananti-fuse trimming architecture for a power IC.

FIG. 7 illustrates an example cross-section of a soft high-voltage (HV)clamp device structure.

FIG. 8 is an equivalent circuit schematic diagram of the devicestructure shown in FIG. 7.

FIG. 9 is an equivalent circuit schematic diagram of the soft HV clampdevice structure shown in FIG. 7 coupled with the integrated devicestructure shown in FIG. 5.

FIG. 10 is an example flow diagram of a sequence of steps forprogramming an anti-fuse element.

FIG. 11 is an example flow diagram of a sequence of steps for reading ananti-fuse element.

FIG. 12 illustrates an example cross-section of another anti-fuse devicestructure.

DESCRIPTION OF EXAMPLE EMBODIMENTS

A novel integrated anti-fuse device structure for use with a newtrimming technology is disclosed. In the following description specificdetails are set forth, such as material types, voltages, structuralfeatures, manufacturing steps, etc., in order to provide a thoroughunderstanding of the disclosure herein. However, persons having ordinaryskill in the relevant arts will appreciate that these specific detailsmay not be needed to practice the embodiments described. Referencesthroughout this description to “one embodiment”, “an embodiment”, “oneexample” or “an example” means that a particular feature, structure orcharacteristic described in connection with the embodiment or example isincluded in at least one embodiment. The phrases “in one embodiment”,“in an embodiment”, “one example” or “an example” in various placesthroughout this description are not necessarily all referring to thesame embodiment or example. Furthermore, the particular features,structures or characteristics may be combined in any suitablecombinations and/or sub-combinations in one or more embodiments orexamples.

It should be understood that the elements in the figures arerepresentational, and are not drawn to scale in the interest of clarity.It is also appreciated that although an IC utilizing mostly N-channeltransistor devices (both high-voltage and low-voltage) are disclosed.P-channel transistors may also be fabricated by utilizing the oppositeconductivity types for all of the appropriate doped regions.

In the context of the present application a high-voltage or powertransistor is any semiconductor transistor structure that is capable ofsupporting 150V or more in an “off” state or condition. In oneembodiment, a power transistor is illustrated as an N-channel metaloxide semiconductor field-effect transistor (MOSFET) with thehigh-voltage being supported between the source and drain regions. Inother embodiments, a power transistor may comprise a bipolar junctiontransistor (BJT), an insulated gate field effect transistor (IGFET), orother device structures that provide a transistor function.

For purposes of this disclosure, “ground” or “ground potential” refersto a reference voltage or potential against which all other voltages orpotentials of a circuit or IC are defined or measured. A “pin” providesa point of external electrical connection to an IC device or package,thereby allowing external components, circuits, signals, power, loads,etc., to be coupled to the internal components and circuitry of thepower IC device.

In the context of the present disclosure a tap transistor is a threeterminal (Le., electrode) transistor device structure in which a voltageat a first or tap terminal is substantially proportional to an appliedvoltage across the second and third terminals when the applied voltageis less than a pinch-off voltage of the transistor device. When theapplied voltage across the second and third terminals exceeds thepinch-off voltage, the voltage provided at the tap terminal issubstantially constant or unchanging with increased applied voltage. Inone embodiment, a tap transistor comprises a junction field-effecttransistor (JFET).

Furthermore, in the context of the present disclosure, an anti-fuse is acircuit element that provides a normally open electrical connection in adevice structure like that of a capacitor, with two or more layers ofmetal, polysilicon, or doped semiconductor material separated by adielectric layer (e.g., oxide, nitride, etc.). The electrical connectionbetween the two layers of metal can be permanently closed by applying alarge voltage across the metal conductors which acts to break down ordestroys the dielectric layer, thereby electrically shorting the twometal layers.

FIG. 1 illustrates an example power IC device block diagram comprising ahigh-voltage output transistor component section 10 that includes one ormore large-sized, high-voltage output transistors which control thecurrent flaw to one or more external loads. In a switch-mode powersupply IC, for example, a single, large, high-voltage output transistormay control the current through the primary winding of a transformer,thereby controlling the power delivered by the power supply. The drainof the high-voltage output transistor is typically connected directly toan external pin.

The conceptual block diagram of FIG. 1 also includes an anti-fuseprogrammable memory 11 coupled to HV output transistor section 10through an isolation transistor element 14. Anti-fuse programmablememory 11 is coupled, in turn, to Read/Write block 12 via an isolationtransistor element 15. Read/Write block 12 is shown being coupled to thecontroller section of the power IC device. Anti-fuse programmable memory11 comprises a series or array of anti-fuse structural elements that maybe programmed through the drain pin of HV output transistor section 10.During programming, isolation transistor element 14 is turned “on” tocouple an externally-applied high voltage to a selected anti-fuseelement of memory 11. At the same time, isolation transistor element 15is turned on for the read/write element associated with the selectedanti-fuse element. All of the other read/write elements of block 12associated with unselected anti-fuse elements are turned “off”. Duringreading of each of the anti-fuse elements in memory 11 isolationtransistor element 14 and isolation transistor element 15 are bothturned on (for all read/write elements in block 12). It is appreciatedthat during normal operation of the power IC device isolation transistorelements 14 and 15 are both off.

FIG. 2 illustrates an example cross-section of an anti-fuse structure 20that may be utilized as a programming element. In one embodiment,anti-fuse structure 20 comprises a tiny (˜10 μm²) gate oxide capacitor32 having a first terminal or electrode 21 (e.g., aluminum, tungstenalloy, or other metals) which connects to an underlying N+ semiconductorregion 23, and a second electrode 22 (e.g., polysilicon) separated fromunderlying N+ region 23 and N-type well region 24 by a thin gate oxidelayer 26, N-well region 24 is shown formed in a P-type substrate 25.

Prior to programming, anti-fuse structure 20 does not pass any current;that is, it appears as an open circuit to a normal D.C. operatingvoltage (e.g., VDD=5-6V). Anti-fuse structure 20 may be programmed(i.e., trimmed) by applying a high voltage pulse across terminals 21 and22 (e.g., 30-35V, 0.5-1.0 mA for 2-5 ms). The voltage required to blowthe anti-fuse will depend on the gate oxide thickness (e.g., ˜30V for 25nm oxide). Application of such a high-voltage pulse causes gate oxide 26to rupture, resulting in a permanent short between electrodes 21 & 22with a resistance typically on the order of a few thousand ohms. Thestate of anti-fuse structure 20 can then be read by sensing itsresistance. As will be described in detail below, the trimming pulseutilized to trim the anti-fuse structure is provided externally throughthe drain pin which connects to the high-voltage output MOSFET device.

Practitioners in the art will appreciate that the amount of currentrequired to trim anti-fuse structure 20 is significantly smaller ascompared to existing zener diodes, which normally require >150 mA.Additionally, persons of skill in the art will understand that theintegrated anti-fuse device structures disclosed herein may reduce theoverall size of the trimming block of a power IC device by a factor ofabout five or more as compared to prior art designs.

FIG. 3 illustrates an example circuit schematic diagram of an anti-fusetrimming architecture for a power IC which comprises an anti-fuse block30 with multiple anti-fuse programming elements 31. Node 36 of anti-fuseblock 30 is shown coupled to node 43 through isolation unit 45. Voltageregulator 44 is coupled between node 43 and ground. Node 43 alsocomprises a first or “tap” terminal of tap transistor 41, which in oneembodiment, comprises a JFET. A second terminal of tap transistor 41 isconnected to an external drain pin or node 42 (labeled V_(EXTERNAL)),which is also connected to the drain of high-voltage output MOSFET 40.The third terminal, the gate of the JFET structure, is normallygrounded. Persons of skill in the semiconductor arts will appreciatethat tap transistor 41 and high-voltage output MOSFET 40 may beintegrated into a single device structure. Also, anti-fuse block 30 andthe controller section of the power IC are normally fabricated on thesame piece of silicon material.

In the embodiment of FIG. 3, anti-fuse block 30 is shown integrating theprogramming memory and Read/Write sections of FIG. 1 into a singlearchitectural block. Anti-fuse block 30 comprises multiple anti fuseprogramming elements 31 ₁, 31 ₂ . . . 31 _(n), where n is an integer.Each anti-fuse programming element 31 is connected between node 36 and acorresponding Read/Write (R/W) block 34 that stores a logical state (“0”or “1”) which reflects the current flowing through capacitive anti-fuse32 and associated MOSFET 33. For example, in the event that anti-fuse 32₁ is not trimmed (i.e., programmed state=“0”), little or no currentflows through anti-fuse programming element 31 ₁. Conversely,application of a high voltage (HV) pulse to trim anti-fuse 32 ₂ producescurrent flow through anti-fuse programming element 31 ₂, (i.e.,programmed state=“1”).

In the example of FIG. 3, a programming or trimming HV pulse may beapplied to the V_(EXTERNAL) pin of the power IC at node 42 andtransferred to anti-fuse block at node 36 through tap transistor 41 andisolation unit 45. In normal operating conditions, isolation unit 45isolates anti-fuse block 30 from the voltage appearing at node 43 of taptransistor 41. To program a selected anti fuse 32, the gate of thecorresponding trimming MOSFET 33 (labeled “AFH_(n)”) is raised to a highpotential and the source is connected to ground (GND) through alow-impedance switch. All of the other trimming MOSFETs (associated withunselected anti-fuses) are off (e.g., gate grounded with their sourcesconnected to ground through a high-impedance). Isolation unit 45 isturned on, which connects anti-fuse block 30 to tap transistor 41.Voltage regulator 44 is turned off during programming to allow node 43(and also node 36) to rise to a relatively high positive voltage. Notethat the pulsed voltage V_(EXTERNAL) applied to the drain pin of thepower IC device may be several hundred volts (e.g., 600-700V), but taptransistor 41 limits the voltage appearing at node 43 to a much lowervoltage potential (e.g., 30-50V). Persons of ordinary skill willappreciate that high-voltage output MOSFET 40 is designed and fabricatedto withstand the high pulsed voltage V_(EXTERNAL) e.g. 600-700V) withoutdamage to the transistor device.

When the high-voltage pulse is applied across the selected anti-fuse 32,the gate oxide separating the two terminals or capacitive platesruptures, thereby programming (shorting) the anti-fuse structure.

For the unselected anti-fuses 32—i.e., the ones that are not intended tobe blown or shorted—the gate of the corresponding MOSFET 33 is groundedsuch that MOSFET 33 is off. Consequently, the voltage appearing at thebottom capacitive plate (connected to the drain of MOSFET 33) rises inpotential, substantially tracking that of the top plate (connected tonode 36). Hence, the gate oxides of the unselected anti-fuses 32 are notruptured and the device structures remain open circuits.

The state of each anti-fuse programming element 31 may be read at thestartup of the power supply, which normally occurs when the VDD powersupply line of the controller section of the IC is first charged.Voltage regulator 44 is turned on at that point so that the maximumvoltage at node 43 is regulated, e.g., under 12V. To read theprogramming state of the array of elements 31 which comprise block 30,the drain pin (V_(EXTERNAL)) is raised to greater than about 10V,isolation unit 45 is turned on, and a small current (severalmicroamperes) is pulled through each of the read/write blocks 34. If aparticular anti-fuse 32 is programmed, the source of the associatedtrimming MOSFET 33 (labeled “AFHn”) floats up to the gate-to-sourcevoltage (Vgs) minus the threshold voltage (Vt) of MOSFET 33. On theother hand, if the particular anti-fuse 32 is untrimmed or open, thesource of the associated MOSFET 33 is at ground potential. The state ofeach anti-fuse programming element 31 is latched in the correspondingR/W block 34 when the VDD voltage potential crosses a certain value(˜5V). Thereafter, isolation unit 45 is turned off, thereby isolatingnode 36 from node 43, and no current flows through anti fuses 32 underthe normal operating condition of the power IC.

FIG. 4 illustrates an example cross-section of one embodiment of ananti-fuse programming element 31 that includes an integratedhigh-voltage field-effect transistor (HVFET) and anti-fuse devicestructure. FIG. 5 is an equivalent circuit schematic diagram of theintegrated device structure shown in FIG. 4. As can be seen theanti-fuse capacitor 32 shown in FIG. 5 comprises a polysilicon layer 48that is separated from an underlying N-type well region 47 by a thingate oxide layer 49 (see FIG. 4). Polysilicon layer 48 and N-well region47 form the two plates of the capacitive anti-fuse structure. N-wellregion 47 also forms the drain region of MOSFET 33. A source electrode58 provides an electrical connection with N+ source region 57 and P+region 56, both of which are disposed in a P-type well region 55 thatadjoins N-well region 47. An area of P-well region 55 which forms thechannel region of MOSFET 33 laterally separates N+ source region 57 fromthe boundary or edge between P-well region 55 and N-well region 47. Thegate of MOSFET 33 comprises a polysilicon layer 52 that is insulatedfrom the underlying P-type substrate 25 and N+ well region by a thingate oxide layer 51. A gate electrode 59 provides an electricalconnection with polysilicon layer 52.

In one implementation, MOSFET 33 is designed to have a breakdown voltageof approximately 50V, whereas gate oxide 49 of the capacitive anti-fusestructure is manufactured to have a breakdown voltage of about 30V.

The device structure of FIG. 4 also includes a first plurality ofsubstantially-parallel, vertically spaced-apart P-type buried regions 53disposed in the left-hand area of N-well 47. A corresponding pluralityof JFET conduction channels 55 are shown formed by the vertical spacingof buried regions 53. A second plurality of substantially-parallel,vertically spaced-apart P-type buried regions 54 is shown disposed inthe right-hand area of N-well 47. Buried regions 53 and 54 are disposedbeneath thick field oxide regions 50. The uppermost buried regions areshown coincident with field oxide region 50 on both the left andright-hand sides of N-well 47.

As can be seen, P-type buried regions 53 and 54 do not extend laterallybeneath thin oxide layers 51 or 49. In one embodiment, a deep implant(not shown) or any other type of equivalent structure may be used toelectrically connect each of buried regions 53 & 54. This allows P-typeburied regions 53 and 54 which comprise the gate of the JFET to beelectrically connected (along with source electrode 58) to a potentialat or near ground when anti-fuse programming element 31 is intended tobe left untrimmed or open.

FIG. 12 illustrates an example cross-section of another anti-fuse devicestructure that is identical in all respects to that of FIG. 4, exceptthat P-type buried regions 53 and 54 are omitted. In other words, it isappreciated that in certain embodiments, P-type buried regions 53 and 54are an optional feature in the integrated anti-fuse device structureutilized in the anti-fuse programming memory described herein.

FIG. 6 illustrates another example circuit schematic diagram of ananti-fuse trimming architecture for a power IC device. Output transistorsection 10 is the same as shown in FIG. 3, with external drain pin(node) 42 being directly connected to the drain of high-voltage outputMOSFET 40 and a second terminal of JFET tap transistor 41. Node 43comprises the first (tap) terminal of tap transistor 41, which is showncoupled to the drain of NMOS HV transistor 71 (labeled N1) of voltageregulator 44. The source of transistor 71 is shown connected to 6Vregulator 73 at node 70, which also comprises an external VDD pin of thepower IC device. In one embodiment, VDD pin 70 comprises the supply pinof the controller section of the power IC device, and voltage regulator44 comprises a shunt regulator that regulates VDD pin 70 to ˜6V.

Node 43 is also shown connected to the source of PMOS HV transistor 78(labeled P1) and to one end of resistor 74 of isolation unit 45. Theother end of resistor 74 (node 75) is shown connected to the gate oftransistor 78, and also to the drain of HV transistor 76 (labeled N2).The drain of PMOS HV transistor 78 is coupled to one end of resistor 79at node 36. The other end of resistor 79 is coupled to the drain of HVtransistor 77 (labeled N3). The sources of transistors 76 & 77 arecoupled to ground.

Practitioners will appreciate that PMOS HV transistor 78 of isolationunit 45 functions to isolate anti fuse block 30 from tap transistor 41under normal operating conditions. Transistor 76 (N2) and resistor 74function to level shift the gate control signal of PMOS HV transistor78. In one implementation, the current through transistor 76 andresistor 74 may be designed such that when the transistor 76 is turnedon, the gate-to-source voltage of PMOS HV transistor 78 is limited toabout 10V. In certain embodiments, the gate of transistor 78 may beclamped.

It should be understood that transistor 77 (N3) and resistor 79 areoptional, and may be used to connect anti-fuse structures 32 to ground.In alternative embodiments, transistor 77 (N3) and resistor 79 may beeliminated so that anti-fuse structures 32 are left floating duringnormal operation.

In one embodiment, isolation unit 45, voltage regulator 44 and trimmingMOSFETs 33 a-33 n (labeled AFH₁-AFH_(n)) are should be capable ofwithstanding the maximum tap voltage (˜50V). For example, the circuitcomponents labeled as high-voltage (HV) devices in FIG. 6 shouldwithstand applied voltages in the 60-70V range before breakdown occurs.

As discussed above, voltage regulator 44 of FIG. 6 is shown coupledbetween node 43 and ground. Node 43 also comprises a first or “tap”terminal of tap transistor 41, which in one embodiment, comprises aJFET. A second terminal of tap transistor 41 is connected to an externaldrain pin or node 42 (labeled V_(EXTERNAL)) which is also connected tothe drain of high-voltage output MOSFET 40.

Continuing with the example of FIG. 6, node 36 of anti-fuse block 30 isshown connected to the drain of PMOS HV transistor 78 and to oneterminal of each of anti-fuses 32 a-32 n. The other terminal ofanti-fuses 32 is coupled to the drain of associated trimming MOSFET 33.The source of each MOSFET 33, in turn, is connected to the drain of anassociated low-voltage (LV) NMOS transistor 82 and a corresponding latchcircuit element 81. The source of each transistor 82 is coupled toground. The gates of all the low voltage NMOS transistors 82 a-82 n(labeled AFL₁-AFL_(n)) are coupled to corresponding Read/Write signallines, whereas the gates of the NMOS (HV) trimming transistors 33 a-33 n(labeled AFH₁-AFH_(n)) are coupled to the output of a decoder (notshown) that selects the trim bit (i.e., which one of the anti-fuses 32is to be blown or trimmed).

To program an individual bit of block 30, the read/write signal linecoupled to the gate of the corresponding LV MOSFET 82 is connected toVDD (˜6V) so that the source of associated trimming MOSFET 33 iseffectively shorted to ground. The gates of all of the other LV MOSFETsare connected to ground, thereby turning these transistors off. By wayof example, to program anti-fuse 32 a, the gate of the LV MOSFET 82 a istaken to VDD, and the gates of MOSFETs 82 b-82 n are grounded.

To read the programming state of anti-fuse block 30, the read/writesignal coupled to transistors 82 is fed from a current mirror such thateach of the LV MOSFETs have few microamps flowing through them.

The example of FIG. 6 also includes optional “soft” HV clamp elements80, each of which is coupled across a corresponding anti-fuse 32. Forinstance, soft clamp element 80 a is coupled across anti-fuse 32 a; softclamp element 80 b is coupled across anti-fuse 32 b; etc. Each of thesoft clamp elements 80 functions to avoid unintentional programming of anon-selected (not selected for trimming) anti-fuse by clamping thevoltage that appears across the corresponding anti fuse 32.Practitioners will understand that when programming a particularanti-fuse, the top plates of all the anti-fuses (node 36) aresimultaneously taken to high voltage of (e.g., ˜50V). When the trimmingMOSFET 33 of an unselected anti-fuse 32 is off, the voltage of the lowerplate (coupled to the drain of the associated MOSFET 33) of anti-fuse 32typically follows the voltage applied to the upper plate via capacitivecoupling, with some small leakage current flowing through the anti-fuse.However, there is a risk that the lower capacitive plate of anti-fuse 32may not track or follow the voltage on the upper capacitive plate, inwhich case the anti-fuse structure may be damaged by the unexpectedvoltage difference between the two plates. To alleviate this potentialrisk, in one embodiment, a parasitic PMOS transistor comprising apolysilicon layer that covers a relatively thick field oxide layer isutilized as a soft HV clamp in parallel to the anti-fuse.

By way of example, the parasitic PMOS transistor utilized as a soft HVclamp may have a threshold voltage (V_(t)) of ˜20V and a BV similar tothat of PMOS HV transistor 78, e.g., 55-60V. The gate of the parasiticPMOS transistor may be connected to ground potential. Duringprogramming, when node 36 of anti fuse block 30 goes higher than thethreshold voltage of the parasitic PMOS transistor, soft clamp element80 begins flowing a small current, e.g., a few microamperes. For theparticular anti-fuse which is being programmed this current will beadded to the trim current that flows through the anti-fuse (500 uA-1mA). For the remaining group of unselected anti-fuses, this low currentcharges the bottom capacitive plate, thereby reducing the voltagebuild-up across each of the unselected anti-fuses. During read cycle,the voltage at node 36 does not exceed ˜12V, so each of soft clampelements 80 a-80 n is off.

FIG. 7 illustrates an example cross-section of a soft high-voltage (HV)clamp device structure comprising a parasitic PMOS transistor 62suitable for use as a soft clamp element 80 in the embodiment of FIG. 6.FIG. 8 is an equivalent circuit schematic diagram of parasitic PMOStransistor 62. FIG. 9 shows transistor 62 coupled with the integrateddevice structure shown in FIG. 5 to implement a soft clamp acrossanti-fuse 32. In the example of FIG. 7, a polysilicon layer 64, whichforms the gate of transistor 62, is shown disposed on a thick fieldoxide layer 66 over the area of N well region 67 between P-type regions68 & 72. N-well region 67 is disposed in P-type substrate 25. It isappreciated that N-well 67 of PMOS transistor 62 is separate from theN-well used to form the anti-fuse structure (e.g., N-well 47 in FIG. 4).An N+ region 70 is also disposed in N-well region 67 to electricallyconnect N-well region 67 to source electrode 63. A P+ source region 69,which is disposed in P-type region 68, is also electrically connected tosource electrode 63. A P+ drain region 71 disposed in P-type region 72is shown electrically connected to drain electrode 65.

It is further appreciated that the gate capacitance of transistor 62 issubstantially lower as compared to the capacitance of anti-fuse 32 dueto the relative thickness of field oxide layer 66. In one embodiment,the threshold voltage of transistor 62, which is largely determined bythe thickness of field oxide layer 66, is approximately 15-20V. Thedrain-to-source breakdown voltage of transistor 62 is greater than 50V.

FIG. 10 is an example flow diagram of a sequence of steps forprogramming an anti-fuse element shown in the embodiment of FIG. 6. Thesequence begins at block 90 with the application of 5V to the externaldrain pin (e.g., node 42 in FIG. 6) of the power IC device. Acounter/decoder may be utilized (e.g., clocked through) to then selectand turn on the appropriate trimming MOSFET 33 (block 91). That is, avoltage is applied to the gate of the trimming MOSFET 33 thatcorresponds to the anti-fuse element selected to be programmed, the gatevoltage being sufficiently high so as to turn on that trimming MOSFET.The other trimming MOSFETs associated with the unselected anti-fuseelements have their gates connected to ground to ensure that they remainoff. The write signal may be applied (block 92) by taking the gates ofthe LV NMOS transistors 82 to VDD (˜6V) thereby shorting the source ofMOSFETs 33 to ground through a low-impedance. Transistors 71 & 77 (N1 &N3) are turned off (block 93), and transistor 76 (N2) is turned on,which causes transistor 78 (P1) to turn on (block 94). Person ofordinary skill will understand that steps 92-95 may be performed in anysequence or order.

The next step in the example sequence shown in FIG. 10 is to pulse drainpin with a high voltage; that is, node 42 is raised to ˜50V and thenlowered back down to 5V (block 95). In one embodiment, a 2 ms durationpulse having a rise time/fall time of ˜100 μs may be applied. Thepost-trim current flowing into the drain pin at node 42 may then bemeasured and compared to the pre-trim current to confirm that theanti-fuse has been properly trimmed.

FIG. 11 is an example flow diagram of a sequence of steps for reading ananti-fuse element in the embodiment of FIG. 6. The read cycle beginswith the raising of the Drain pin (node 42) to higher than about 10V(block 110). Next, transistor 71 (N1) of voltage regulator 44 is turnedon (block 111), transistor 77 (N3) is turned off (block 112), andtransistor 76 (N2) is turned on (block 113). Turning on transistor 76has the effect of also turning on transistor 78 (P1), thereby turning onisolation unit 45. All of trimming MOSFETs 33 a-33 n are then turned on(block 114).

At this point a read signal may be applied to the gates of transistors82 a-82 n such that a small current (˜several microamperes) issimultaneously pulled through each leg of anti-fuse block 30 (block115). For example, the read signal coupled to the gates of transistors82 may be fed from a current mirror to establish the small current flowthrough transistors 82 for purposes of reading the state of each antifuse 32. In this configuration, the sources of each of the trimmingMOSFETs 33 are essentially connected to ground through a high-impedance.In the event that a particular anti-fuse 32 is programmed, the potentialat the source of the associated trimming MOSFET 33 floats up to thedifference between the gate-to-source voltage (Vgs) and the thresholdvoltage (V_(t)) of the associated trimming MOSFET 33. In other words,the voltage at the source (Vs) of a particular MOSFET 33 associated withan anti-fuse element 32 that has been blown (programmed) is Vs=Vgs−Vt.On the other hand, if a particular anti-fuse 32 remains open (notprogrammed), then the source of the associated trimming MOSFET 33 is ator near ground potential.

After the read signal has been applied to anti-fuse block 30, the sourcevoltage of each of trimming MOSFETs 33 may be latched (stored) incorresponding latch element 81 (block 116). In one embodiment, latchingof the state of each anti-fuse programming element occur when the VDDpin (node 70) crosses 5V. Latch element 81 may comprise any one of anumber of well-known latch circuits or devices, e.g., an ordinarySet/Reset (R/S) latch. After the source voltages of each MOSFET 33 havebeen latched in each of the corresponding latch elements 81, transistor76 (N2) is turned off, thereby turning off transistor 78 (P1).Transistor 77 (N3) is also turned on. These later steps effectively turnoff isolation unit 45, causing anti-fuse block 30 to be isolated fromthe voltage produced by tap transistor 41 at node 43, therebytransitioning the power IC device back to a normal mode of operation.

Although the present invention has been described in conjunction withspecific embodiments, those of ordinary skill in the arts willappreciate that numerous modifications and alterations are well withinthe scope of the present invention. Accordingly, the specification anddrawings are to be regarded in an illustrative rather than a restrictivesense.

1-14. (canceled)
 15. A method for reading a programmable anti-fuse blockof a power integrated circuit (IC) comprising: providing a first voltageat a common node of the programmable anti-fuse block, the common nodebeing coupled to a plurality of anti-fuses, each anti-fuse having aprogrammed state; generating a read signal that turns on a plurality ofselector switches, each selector switch being coupled to a correspondingone of the anti-fuses; and latching a voltage potential at a second nodeof each selector switch, the voltage potential being representative ofthe programmed state of each anti-fuse.
 16. The method of claim 15further comprising reading the latched programmed state of eachanti-fuse by a controller of the power IC.
 17. The method of claim 15further comprising decoupling the programmable anti-fuse block from thefirst node.
 18. The method of claim 15 wherein each selector switchcomprises a field-effect transistor (FET) having a drain coupled to acorresponding one of the anti-fuses, each selector switch also having agate and a source.
 19. The method of claim 15 further comprisingapplying an external voltage to a pin of the power IC, the pin beingcoupled to circuitry that lowers the external voltage to the firstvoltage at a common node.
 20. The method of claim 19 wherein thecircuitry comprises a tap transistor element.
 21. The method of claim 19wherein the circuitry comprises a level shift transistor.
 22. The methodof claim 15 wherein the read signal is generated by the controller.